1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing the semiconductor devices.
2. Description of the Related Art
Recently, various types of circuits are often formed using thin film transistors (hereinafter, referred to as TFTs) over one substrate. In order to form various circuits using TFTs, attention should be given to that TFTs having different structures each of which corresponds to each of the circuits should be formed. This is because, considering the case of a display device, operating conditions of a TFT in a pixel portion and those of a TFT in a drive circuit are not always the same, and characteristics of TFTs which should also be different.
TFTs in a pixel portion which includes n-channel TFTs apply voltage to and drive liquid crystal as switching elements. The TFT in a pixel portion needs to have a sufficiently low OFF current value in order to hold charge accumulated in a liquid crystal layer during one frame period. On the other hand, since a buffer circuit and the like in a driver circuit are applied with a high drive voltage, it is necessary to increase a withstand voltage so that elements in the driver circuit are not broken even when the elements in the driver circuit are applied with high voltage. In addition, in order to enhance ON current drive capability, it is necessary to secure a sufficient ON current value.
As a structure of a TFT which reduces the OFF current value, a structure having a low-concentration impurity region (hereinafter also referred to as an LDD (lightly-doped drain) region) is given. Such a structure has a region to which an impurity element is added at a low concentration between a channel formation region and a source region or a drain region to which an impurity element is added at a high concentration.
Further, as a means for preventing degradation in ON current value due to hot carriers, there is a structure in which an LDD region is formed to overlap with a gate electrode with a gate insulating film interposed therebetween (such a structure is referred to as a gate overlapped LDD (GOLD) structure in this specification). With such a structure, a high electric field in the vicinity of a drain is relieved; therefore, degradation in ON current value due to hot carriers can be decreased. Note that in this specification, a region in an LDD region which does not overlap with the gate electrode with a gate insulating film interposed therebetween is referred to as an Loff region, while a region in the LDD region which overlaps with the gate electrode with the gate insulating film interposed therebetween is referred to as an Lov region.
Note that the Loff region have high effect on suppressing the OFF current value, whereas the Loff region has low effect on preventing degradation in the ON current value due to hot carriers by relieving the electric field in the vicinity of the drain. On the other hand, the Lov region works effectively in preventing degradation in ON current value by relieving the electric field in the vicinity of the drain; however, it does not work effectively in suppressing the OFF current value. Thus, it is necessary to form a TFT having a structure having characteristics in need for each of the various circuits.
Further, as to On current, there is also a method in which a contact resistance, which is parasitic resistance of a TFT, is decreased so that ON current is increased. In specific, nickel silicide is provided in a source region and a drain region to decrease contact resistance with a wiring (for example, see Patent Document 1: Japanese Published Patent Application No. 2006-156971).